The design library
Every primitive in the Periodic Stack compiles to a concrete design — and every one of them builds. Not “is specified”, not “is emittable”: each artifact is put through the real tool for its format on every run.
The last number is the point. The substrate is chosen by the math, not by habit — digital logic is where a primitive lands when the physics offers nothing better, not the default. See what reached silicon →
What “builds” means here
No self-reported status. Each format is checked by the tool that would reject it.
| format | designs | checked with |
|---|---|---|
| loading… | ||
Beyond building: does it compute the right function?
Building is the floor. A design can compile and still compute the wrong thing — so each is checked against its primitive's definition, and where two primitives share a circuit it is because the math genuinely coincides, said plainly in the design's own header.
- Verilog — differential simulation vs an independent reference (iverilog)
- Reversible — exhaustive: every input, correct output and a bijection
- Analog — ngspice checks the actual transfer function (ramp slope, product, log law, noise)
- Rust — known-answer tests against published vectors
- Photonic / QASM — the emitted operator is the primitive's, one design per primitive
bash scripts/verify/measure_scan.sh # prefix scan, bit-exact
bash scripts/verify/measure_yates.sh # Möbius∘zeta = identity; Ryser permanent
bash scripts/verify/validate_analog.sh # 42 decks → right transfer function
bash scripts/codec/measure_arith.sh # arithmetic coder, bit-exactThe audit caught real defects — a “scan” that was a reduction, a “permanent” that was a subset-sum, an RNG with no entropy — and each was fixed, not papered over.
Browse every design
- loading the catalog…
Pick a primitive on the left. Its design is emitted by the live API — the same bytes you would get from
GET /api/v2/foundry/emit/{id} — and it is the design that was compiled to produce the 265/265 above. Honest boundary: “builds” is not “taped out.” These designs compile, lint and parse. The ones additionally carried through place-and-route to DRC-clean, LVS-matched silicon are named on Measured silicon. Building is the floor, not the finish line.