Measured silicon
The Periodic Stack in measured silicon — every value below is a real measurement or physics simulation on SkyWater sky130 (open PDK); photonic on CORNERSTONE si220. Nothing here is a spec sheet: the tool that produced each number is named, and device budgets (photonic optical, acoustic transduction) are labeled as such.
sky130_fd_sc_hd tt_025C_1v80, 100 MHz / 0.2 activity reference · as of 2026-07-07
Read the thesis — one law across every substrate →From a math table to a tapeable die
| stage | result | tool |
|---|---|---|
| 1. Coverage | 265/265 REAL, 0 stubsevery primitive emits a buildable, verified artifact | emit + iverilog/verilator |
| 2. Architecture | 265 → 135 cores → 8 chiplets → 1 SiPthe stack collapses onto shared cores | architecture example |
| 3. Area | 871 – 62,595 µm² (mean 0.016 mm²)real standard-cell area of the cores | sv2v → yosys → sky130 |
| 4. Power | 0.44 pJ – 1.67 nJ/opreal gate-level power → joules/op | OpenROAD/OpenSTA report_power |
| 5. Energy (6 substrates) | analog 16.7 fJ/tanh · reversible 4600×↓ · PIM 0.66 fJ/MAC · acoustic verifiedper-substrate energy measured/simulated | ngspice / FDTD / gdsfactory |
| 6. Layout | routed, +0.5–44% interconnect power taxRTL → placed & routed | OpenROAD PnR |
| 7. Signoff | DRC 0/145 clean; LVS 771=771 devices, all cells matchrouted → tapeable GDS → DRC + LVS | KLayout + magic/netgen |
The substrate axis
Six ways to run the same math. Each measured or simulated on real physics.
Commodity CMOS (baseline)
measured0.44 pJ – 1.67 nJ/op across 17 synthesized cores; leakage <0.01% (toggle-dominated)
caveat: the reference rung — the physics model is validated in shape by the measurement
yosys + OpenSTA · MEASURED_POWER.md
Analog translinear
measured16.7–165 fJ per tanh (2 transistors); energy = VDD·Ibias·τ_settle
caveat: model's 0.1 fJ/op was optimistic ~1000×; SNR trades linearly with energy
ngspice + sky130 devices · ANALOG_ENERGY.md
Adiabatic / reversible
measureddissipation ∝ 1/T; 4600× below ½CV²=162 fJ at a 10 µs ramp
caveat: the 1000× is reachable but buys energy with time; a naive nfet pass gate floors at ~4×
ngspice + sky130 devices · REVERSIBLE_ENERGY.md
Photonic MZI mesh (flagship)
layout-measured + budget54 linear primitives → 1 Clements mesh; 32×32 = 496 MZIs / 992 phase shifters / ~4.24 mm² (real cells)
caveat: layout measured; energy is a device BUDGET — MACs passive (~free), but ~10 W thermal hold (PCM deletes it) + ~30 fJ/MAC ADC
gdsfactory + CORNERSTONE · PHOTONIC_ENERGY.md
Processing-in-memory (ReRAM crossbar)
measuredMAC exact (0.00% vs digital) at 0.66 fJ/MAC — Ohm's law + Kirchhoff in the wire
caveat: IR drop caps the usable array at ~16-32 rows; per-column ADC (~tens fJ/MAC) is the real floor
ngspice resistor crossbar · PIM_ENERGY.md
Acoustic SAW convolver
simulateda convolution in one wave transit; 8/8 FIR tap signs + 0.949 corr vs digital
caveat: energy transduction-dominated (IDT 6–20 dB IL); an analog-delay/matched-filter substrate, not a MAC array
1-D elastic-wave FDTD · ACOUSTIC_ENERGY.md
The representation axis
Same primitives, different number system — different operation gets cheap. All measured on one process.
| encoding | measured | makes cheap |
|---|---|---|
| ternary {−1,0,+1} | 1.11 pJ/MAC | the MAC — no multiplier (~4× under int8) |
| int8 (baseline) | 4.22 pJ/MAC | — (plaintext reference) |
| LNS (log domain) | 3.14 pJ × (vs 7.20 real ×) | the multiply → an adder; add → a Gaussian-log LUT (4.38 pJ), ~4-5 bit |
| FHE (encrypted) | 26 / 92 / 214 / 286 pJ per butterfly (W=16/32/48/64) | nothing — buys privacy; NTT+modmul, the universal FHE/ZK datapath |
Measured cores
Real sky130 synthesis + OpenSTA power at 100 MHz — energy/op = P × period.
| core | area µm² | power mW | E/op pJ |
|---|---|---|---|
| model_check | 871 | 0.069 | 0.69 |
| lattice_meet_join | 1,602 | 0.044 | 0.44 |
| dfa_run | 2,622 | 1.31 | 13.1 |
| greedy_color | 3,157 | 0.549 | 5.49 |
| transitive_closure | 3,925 | 0.797 | 7.97 |
| tree_reduce | 6,497 | 3.42 | 34.2 |
| union_find | 8,795 | 41.8 | 418 |
| persistent_homology | 14,196 | 42.3 | 423 |
| lbm_d1q3_step | 14,853 | 2.36 | 23.6 |
| gale_shapley | 15,226 | 27.1 | 271 |
| csg_eval | 21,501 | 3.75 | 37.5 |
| sort_net | 35,904 | 24.6 | 246 |
| ac3_propagate | 46,069 | 8.03 | 80.3 |
| auction | 62,595 | 167 | 1670 |
On every substrate the compute is nearly free in the physics; the true cost is data conversion at the boundary plus a physical scaling limit.
- DATA CONVERSION at the boundary: ADC/DAC, E/O–O/E, IDT transduction (ADCs are 60–80% of in-memory-compute energy in the literature)
- a PHYSICAL SCALING LIMIT: IR drop, thermal hold, settling time, device mismatch, insertion loss
The design problem is not the compute substrate — it is minimizing conversions (stay in one domain) and pushing the scaling limit. The substrate leverage is a ratio, so it survives every absolute-model correction the measurements forced.
Compute-aware conversion: match ADC precision to what the analog actually delivers.
Two limits couple — IR-drop caps the crossbar's delivered bits as the array grows (measured: 6.15 b at N=8 → 0.10 b at N=128), and ADC energy doubles per bit. Never convert past the bits the array can produce, and size the array at the IR-drop knee.
Co-design optimum (4-bit compute): a 16×16 tile with a 4-bit ADC → 10.7 fJ/MAC, ~396× below the measured int8 digital MAC — honestly bounded by 4-bit precision and the array-size limit.
Optimizing conversion energy alone drives the array to 128×128 (20.7 fJ/MAC) — where it delivers 0.1 effective bits. You spend 8-bit ADC energy digitizing noise.
Reproduce any number: the scripts and docs live in the openie-fpga
foundry crate (scripts/{fhe,logmath,pim,acoustic,spice},
synth_power.sh, pnr_sweep.sh) and
cargo run --example energy prints this whole landscape.